Layout Design Engineer 版图设计工程师

招聘人数：1 人 性别要求：不限性别 Position Overview:　 Responsible for IC full-custom analog layout, verification of the layout （DRC/ERC/LVS）, RC extraction for post simulation
Responsibilities:　 Primary （70%）: 1.Full custom analog layout/verification an d RC extraction. 2.Perform block level layout. Conduct physical verification （DRC an d LVS using Cadence tools）.
Secondary （30%）: 1.Team work with analog designers, optimize layout. 2.Perform floor planning an d placements （pad locations an d custom routing）.
Requirements:　 1.Bachelor Ｏr above degree with 5 years experiences in CMOS IC full-custom layout.2.Experiences in Mixed signal/analog/high speed layout.3.Familliar with layout skills an d knowledge is must.4.Good teamwork/communication/positive is must.5.Familiar with Cadence IC layout an d verification tools6.Having massive IP block experiencePlus:1.Familiar with 0.18/0.13/0.09/0.065/0.04 um CMOS process an d design rule is a plus.2.Familiar with ESD/Latch up/antenna an d related layout solutions is a plus.3.Familiar with layout size reduction is a plus, with standard cell experience is good.4.Familiar with rule deck is a plus.